Address transformation circuit arrangement

摘要

Two circuit arrangements are described for transforming 2n global addresses used in a control engineering system having several local units into 2m local addresses used in one of the units of the system. One of these contains several memories in which subfunctions resulting from a splitting of the transformation function conveying the transformation are stored. The other circuit arrangement contains a single memory which accepts all subfunctions. The transformation function is split into the subfunctions in such a manner that an optimum compromise is achieved between the storage space required for storing the subfunctions and the time required for the transformation.