| 摘要 |
Device for the testing and checking of the operation of blocks within an integrated circuit, characterized in that it is formed from a set of shift registers and logic circuits associated with each block of the circuit to be tested, the set of registers including at least one test register (35), one status register (36) and one mask register (37), the status register (36) being connected to the outputs (ST0 to ST15) of the block to be tested while the test and mask registers (35,37) and the logic circuits (38,39) are connected to a central processing unit (1) of the integrated circuit of which the blocks form part, the central processing unit (1) being also connected to the said blocks (7,10) by a common interrupt line ( SIGMA INT).
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