| 摘要 |
An exclusive OR gate associated with counting stages causes the counter to generate pseudo-random number sequences. A scrambler- encoder also has an input and a number of counter stages for counting code lengths. A scramber also break up any character strings of all ones or zeros. The counter is driven by a master clock input on line. A parity check generator generates parity bits. A switching logic determines periods during which the output will receive scrambled data and when it will receive parity bits. This apparatus performs both encoding and scrambling steps simultaneously, and is suitable for inter-computer sattellite communication networks.
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