| 摘要 |
PURPOSE: To obtain a CMOS for both high and low voltages which is made of a single-level polysilicon and has a single gate oxide thickness by using individually low-level doped drain regions for high voltage N-channel devices. CONSTITUTION: On a P<+> -type substrate 1, an epitaxial layer 3, P<-> -type well 2, adjacent N<-> -type tank 4, furthermore a field oxide 5 and a gate oxide 7 are formed. Polysilicon gates 9, 11 are formed on the gate oxide. Between the gate oxide and field oxide source regions 15, 19 drain regions 13, 17 are defined, and P is implanted at about 4×10<12> /cm<2> density, without mask. Using a photoresist 29, P is implanted at 2×10<13> /cm<2> density in a high-voltage N- channel device, except the drain regions. A side wall oxide 30 is formed. A photoresist 31 is provided on P-channel transistors, P is implanted at 4×10<14> /cm<2> to form N<+> source/drain regions of N-channel high voltage-low voltage transistors.
|
