| 摘要 |
<p>PURPOSE:To reduce the clock skew caused between units and to increase the system working speed by adding a variable delay circuit into a clock signal distributing path reaching up to a load circuit from the input of a unit. CONSTITUTION:When an oscillation loop selecting signal is outputted from a service processor SVP4, an oscillation loop is formed in a unit 30 to return a selector circuit 7 via a variable delay circuit 8, a four-phase clock generating circuit 9, a clock distributing circuit 23a and a load circuit 24a. Then the output value of the oscillation loop is obtained to a fixed counting time of a reference clock for each of units 3b, 3c, etc. These loop count values are compared with each other. The circuit 8 is controlled so that the loop count values are equal to each other among those units.</p> |
