发明名称 DATA PROCESSOR
摘要 <p>PURPOSE:To secure the even action timing among circuits by stopping a reference clock for a prescribed period to the corresponding circuit constitution part when the deviation of the action timing is detected among the circuit constitution parts. CONSTITUTION:A clock pulse 21 is applied to a clock inhibiting circuit 41 and also to NAND circuits 43 and 44 via an inverter 42 respectively. While a clock pulse 22 is applied to the circuit 41. The circuit 41 incorporates a control means to supply the status signals 25a and 25b showing the working state of a CPU as well as the status signals 26a and 26b showing the working state of a DMAC 15. Thus the control means monitors the deviation of the action timing between the CPU and the DMAC. If the deviation of the action timing is detected, a reference clock is stopped for one period to the corresponding device.</p>
申请公布号 JPS6458006(A) 申请公布日期 1989.03.06
申请号 JP19870214154 申请日期 1987.08.29
申请人 TOSHIBA CORP 发明人 UMEDA AKIRA;MIZUTANI MOTOHARU
分类号 G06F13/42;G06F1/04;G06F1/12;H04L7/00 主分类号 G06F13/42
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