| 摘要 |
PURPOSE:To reduce the consuming power of a SRAM, by dividing the memory cell array of the SRAM into 32 in the direction of a column and disposing a row recorder circuit in the central part thereof. CONSTITUTION:In the SRAM, the memory cell array is divided into at least 32 in the extending direction of a word line, the row decoder circuit R-DC is disposed at the center part thereof and a column switch CSW, a column decoder circuit CDC, etc., are disposed on the one end part of the individual divided memory cell arrays. External terminals P are disposed at the four sides of rectangular semiconductor chips constituting the SRAM and the two sets of the column switches CSW are controlled by one column decoder circuit CDC. Thereby, the quantity of a current passing from a load circuit to the memory cell can be reduced to 1/32 to reduce the consuming power of the SRAM and attain the high speed of the operating speed of the SRAM. |
