| 摘要 |
PURPOSE:To shorten the wiring length of a signal line, to reduce its resistance and to suppress the phase displacement of a signal by providing signal connecting cells disposed at positions becoming a linear state between cell rows and intercell wirings having wider wiring width than the normal wiring for connecting the signal connecting cells. CONSTITUTION:Wirings 21 are formed of input side wirings 17 having a wider wiring width in signal connecting cells 13 and intercell wirings 14. A clock signal output from a clock driver cell 15A is transmitted through wirings 21 to cell row positions. The wiring width is wide, and linearly extended, the wiring length is minimized. Accordingly, its resistance value is sufficiently reduced. Since a clock signal is supplied from the cell 13 through cell row wirings 16 provided corresponding to the cell rows to a standard cell 22, such as a flip-flop cell (F/F) necessary for the clock signal in the cell rows, the wiring length of the wirings 16 having normal wiring width can be minimized. |
