| 摘要 |
PURPOSE:To operate the whole processing system under a virtual computer system, by providing first and second processors, and providing a base address guard register (BAGR) on the second processor. CONSTITUTION:An accessible area by a vector unit 2 being the second processor is set extending from the highest rank address of a storage device 4 to a VU domain 10, so that the accessible area can be designated by only the contents of a BAGR 8. Accordingly, when the unit 2 executes an access, a memory access exception can be detected by only comparing a system absolute address of a result obtained by converting a logical address by an address converting mechanism, and the contents of the BAGR 8. That is, at the time of executing an operation as a virtual computer, the memory access exception can be detected, therefore, the whole processing system operated together with a scalar unit 1 being the first processor and a channel processor 3 can be operated under the virtual computer system. |
