| 摘要 |
<p>A symmetrical amplifier (26) for adjusting the logic levels used in ECL logic to the logic levels used in CMOS logic comprises first and second parallel branches between the supply voltage lines (16, 14), both branches comprising NPN transistors connected as emitter followers (30, 32). Their base electrodes are connected to the input signal lines and their emitters are connected in series with two PFET's (38, 40) in common gate configuration and DC biased by a DC biasing circuit (28). The symmetrical amplifier further comprises a symmetrical load (33) comprising flip-flop (42, 52, 44, 54) and active loads (43, 45) for speeding up the commutation thereof. Two output circuits (48, 49) and (50, 51) are driven by the nodes (52, 53) of the flip-flop and provide CMOS compatible levels at their outputs (54, 55).</p> |
