发明名称 LOGIC CIRCUIT FOR MULTIPLIER
摘要 PURPOSE:To realize multiplication with optional accuracy and without using any complicated circuit for rounding, by supplying the rounding signal produced with an optional bit to a multiplication/addition unit circuit set at the preceding stage so that a rounding is carried out with an optional bit. CONSTITUTION:The rounding addition is carried out in the same way as the production of a partial product when '1' of the rounding signal is added to a sum input terminal 34 led from the preceding stage of the multiplication/ addition unit circuits B23, 26 and 29 set at the preceding stage where the multiplicand data is inputted. The rounding signal is produced by the bit selected by a round signal generating circuit 45 after the rounding control signals are received from the rounding control input terminals 43 and 44. As a result, the rounding position can be optionally changed by the rounding control signal and therefore the number of valid bits of the desired result of multiplication is also changed optionally.
申请公布号 JPS6453228(A) 申请公布日期 1989.03.01
申请号 JP19870208347 申请日期 1987.08.24
申请人 MITSUBISHI ELECTRIC CORP 发明人 YOSHIDA TOSHIHIRO
分类号 G06F7/53;G06F7/38;G06F7/483;G06F7/508;G06F7/52 主分类号 G06F7/53
代理机构 代理人
主权项
地址