发明名称 |
PRECHARGING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE |
摘要 |
PURPOSE: To attain a high speed reading operation following a writing operation by starting pre-charging with a pulse produced from a write enable signal before pre-charging with a pulse produced from an address fluctuation detector. CONSTITUTION: When a writing operation is changed to a reading operation, N channel MOS transistors 16 and 17 are turned ON by a pulseϕWE produced by a write enable signal and a bit line BL and the inverse BL are charged to specified levels. Then, the bit line BL and the inverse BL are completely pre-charged in transistors 11 to 13 which respond to a pulse inversion EQ produced from an address fluctuation detector (ATD). Transistors 14 and 15 are always turned ON by high resistance and a current for compensating for the leaked amount from the bit line during a long cycle is supplied. Thus, by performing pre-charging in two stages, a high speed for a reading operation following a writing operation is attained.
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申请公布号 |
JPS6452282(A) |
申请公布日期 |
1989.02.28 |
申请号 |
JP19880153688 |
申请日期 |
1988.06.23 |
申请人 |
SAMSUNG SEMICONDUCTOR & TELEOMMUN CO LTD |
发明人 |
BIYUN YUN KIMU;TE SUN JIYUN;SAN KI WAN |
分类号 |
G11C11/41;G11C11/40;G11C11/419 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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