发明名称 Clock signal generating circuit for television receiver
摘要 A clock signal generating circuit for a television receiver, which generates a composite synchronizing signal and a masking signal for controlling the operation of the circuit, the composite synchronizing signal including at least two partial signals. The circuit includes a voltage controlled oscillator for generating an output oscillation signal having a predetermined frequency, a source for supplying a reference voltage corresponding to a predetermined center frequency of the oscillation signal to the oscillator, a phase comparator for comparing the phase of the oscillation signal output from the oscillator with the phase of one of the two partial signals and generating a phase error signal corresponding to the difference in phase between the oscillation signal and the one of the two partial signals for adjusting the frequency of the oscillation signal, a circuit responsive to the masking signal for interrupting the comparison by the phase comparator for a period of time corresponding to the period of another one of the two partial signals, a switch for interrupting the supply of the reference voltage to the oscillator during the period when the mask circuit is interrupting the comparison, and a device for maintaining the voltage supplied to the oscillator at a level corresponding to the voltage supplied at the time of the interruption by the switch and the mask circuit.
申请公布号 US4809068(A) 申请公布日期 1989.02.28
申请号 US19880157385 申请日期 1988.02.18
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NAGAI, HIROSHI
分类号 H04N5/05;H03J7/02;H03L7/089;H03L7/095;H04N5/12;(IPC1-7):H04N5/04;H04N5/06 主分类号 H04N5/05
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