发明名称 |
ANORDNING FOER OEVERFOERING OCH BEHANDLING AV DATA ELLER SIGNALER I EN GRUPP AV MULTIPLEXLEDNINGAR. |
摘要 |
A data and signaling time slot transfer and processing system for a set of multiplex lines comprises a switching matrix. Its inputs are connected to n multiplex lines by switching matrix input lines. There are m serial communication controllers each connected to an input register and an output register. The outputs of the switching matrix are connected by m output lines to the input registers. Its inputs are connected by m input lines to the output registers. The matrix outputs are also connected by n switching matrix output lines to multiplex lines. A composite clock signal is applied to all the input and output registers. A further clock signal is applied to the controllers, for the purpose of changing the information reception and transmission bit rates, the information having a bit rate of 64 kbit/s and the multiplex lines functioning at 2.048 Mbit/s. |
申请公布号 |
FI78204(B) |
申请公布日期 |
1989.02.28 |
申请号 |
FI19840003569 |
申请日期 |
1984.09.12 |
申请人 |
COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL |
发明人 |
BOULARD, PIERRE;GOURIOU, ROGER |
分类号 |
H04J3/00;H04L29/02;H04Q11/04;(IPC1-7):H04J3/08 |
主分类号 |
H04J3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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