| 摘要 |
PURPOSE:To reproduce an analog audio signal without being susceptible to input data jitter or the like by using a clock signal of a sampling frequency generated by a PLL circuit so as to convert the audio data into the analog signal. CONSTITUTION:A sampling signal with less jitter synchronously with a 2nd PLL circuit 8 of a narrow band PLL circuit with high accuracy, that is, an output from a preset frequency divider 12 is fed to a D/A converter 14 via a changeover switch 13. Then the audio data processed by a signal processing circuit 7 is converted into an analog signal in the timing of the sampling signal with less jitter generated in the 2nd PLL circuit 8 by the converter 14 resulting in reducing the modulation due to jitter onto the audio signal. |
