发明名称 PLL CIRCUIT
摘要 PURPOSE:To expand a capture range by controlling a voltage control oscillator also by the output of a frequency comparator in addition to the output of a phase comparator. CONSTITUTION:When a frequency difference between an 8/10 signal inputted from a terminal 1 as a reference input and a demodulating clock as a variable input is stored in the 1st capture range, a phase comparator 3 compares both the inputs and outputs an error signal having size and polarity corresponding to the shear, quantity and directions of the phases. When said frequency difference is stored in the 2nd capture range wider than the 1st range, a frequency comparator 4 compares both the values and outputs the shear or the like of frequency as a signal. High frequency components are respectively removed from signals obtained from comparators 3, 4 by the 1st and 2nd LPFs 5, 6, inputted to an adder 7, controlled by the oscillation frequency of a voltage control oscillator 8 and outputted from a terminal 2 as a demodulated clock.
申请公布号 JPS6449176(A) 申请公布日期 1989.02.23
申请号 JP19870205015 申请日期 1987.08.20
申请人 PIONEER ELECTRON CORP;HITACHI LTD 发明人 INOHANA HARUYUKI;SAKAMOTO SHUNICHIRO;TAKADA HIDEAKI
分类号 H04L7/033;G11B20/14;H03L7/08;H03L7/087;H03L7/113 主分类号 H04L7/033
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