| 摘要 |
This circuit arrangement makes possible direct access to the interrupt signal-receiving input of a central control device, even by simultaneously present request signals of peripheral devices. So-called vector bits are put on a data bus on the occurrence of an acknowledgment signal, which is associated with a priority signal, so that a processing level within a priority level can be recognised by the central control device, and the events can be processed successively according to a predefined scheme.
|
