| 摘要 |
An analog to digital converter circuit includes encoder circuitry (18) which employs a dummy bit line (25) to derive timing signals employed in establishing (in 20) stable, valid output digital signal information. For almost all binary codes of interest, the dummy bit line employed may actually comprise a portion of an otherwise unused bit line. A converter embodying the invention may employ a clocked regenerative bit line sustainer circuit driven by dummy bit line derived timing signals. Additionally, the converter also preferably employs a folded antiparallelf architecture in which the bit lines are disposed in a generally U-shaped arrangement surrounding the parallel segments along their outer edges. |
