| 摘要 |
PURPOSE:To decrease area per cell and make possible higher integration by performing all of the separation between memory cells using a bit line commonly by p-n junctions. CONSTITUTION:A deep (n') type region 20 for separation is formed at the center of a shallow n<+> type region 12 connected to a power source line VCC and a deep n<+> region 28 for separation reaching the surface of a substrate 2 is also provided right under the central part of the region 10 connected to a bit line BL. The region 28 is formed by same ion implantation process as that for the region 20. A source- drain region 10 connected to the bit line of adjacent cells Q2, Q3 is used commonly, and the contact hole 26 of the region 10 and the bit line BL is one, thus the cell area is decreased. When in operation the bit line BL is set at 0V and the word line WL2 at positive potential, a channel inversion layer is formed only on the surface of the p type region 4a of the cell Q2 and when gate voltage is turned off, the channel disappears and the charge in that channel is injected into the region 4a. |
