| 摘要 |
<p>The memory access control device to be used to access a memory organized in 2<n> byte words and having the capability of addressing each byte in a word under control of byte select signals (BS), through a m-byte large bus 22, with 2<n>/m being an integer k, to write or read data byte bursts comprising a variable count of bytes. To perform a write operation, k sets of m bytes received from bus 22 are stored into 2<n> registers 40 during each bus period T, and then they are transferred into buffer 30 which comprises successive location of 2<n> bytes positions, through an alignment and control logic 42, which causes the buffer to be written in such a way that it maps the data arrangement in memory, which depends upon the least significant bits of the memory starting address determining the byte location within the memory words. Once the complete data burst is written into the buffer, the buffer content is transferred to the memory by selectively activating the byte select signals according to the least significant bit values and the byte count value. To perform a memory read operation, the data read from the memory are transferred from the memory to the buffer in such a way that the buffer content maps the data burst arrangement in the memory. Then, the buffer is read and the data bytes read from each buffer location are provided to the registers 40. The data register content are provided through the alignment and control logic 42 to the data bus in the rigth order. This device allows to take full advantage of the page mode facility of dynamic memories, since it allows successive adjacent words to be addressed during the burst transfer.</p> |
