发明名称 Bi-mos circuit capable of high speed operation with low power consumption.
摘要 <p>A Bi-MOS circuit includes an input terminal (11), an output terminal (12), an N-channel MOS transistor (14) having a gate connected to the input terminal, a source connected to the ground and a drain, an NPN bipolar transistor (17) having a collector connected to a first power voltage line (VCC), an emitter connected to the output terminal (12) and a base connected to a drain of the N-channel MOS transistor (14), a load element (13) connected between the base of the NPN bipolar transistor (17) and a second power voltage line (VCC) lower than the first power voltage line and a switching element (15, 18) connected between the output terminal (12) and the ground and having a control electrode connected to the input terminal (11), the switching element connecting the output terminal and the ground when a first level of input signal turning the N-channel MOS transistor (14) on is inputted to the input terminal (11) and disconnecting the output terminal (12) from the ground when a second level of the input signal turning the N-channel MOS transistor (14) off is inputted to the input terminal.</p>
申请公布号 EP0304035(A2) 申请公布日期 1989.02.22
申请号 EP19880113356 申请日期 1988.08.17
申请人 NEC CORPORATION 发明人 YAMAZAKI, TORU
分类号 H03K19/00;H03K19/0944 主分类号 H03K19/00
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