发明名称 TROUBLE DETECTION SYSTEM
摘要 PURPOSE:To discriminate an LSI of the trouble occurrence source by providing a clock machine which stops update at the time of trouble detection and stopping update also at the time of trouble detection in the other highly integrated circuits constituting a device. CONSTITUTION:Highly integrated circuits LSI 1 and LSI 2 are provided with counters 1 and 2 which simultaneously count a clock (CLK) synchronously with each other. If the counting operation of the counter 1 is stopped by trouble detection in the LSI 1 and the counted value at this time is '00100', pertinent trouble data is propagated to the LSI 2 and trouble is detected similarly, and the counter 2 counts one clock extra and is stopped with counted value '00101' when the counting operation of the counter 2 in the LSI 2 is stopped. Since counting operations of counters 1, 2... in LSIs 1, 2... constituting the device are stopped when a freeze signal is sent from a trouble freezing circuit of the device including LSIs 1, 2... in this state, it is recognized that trouble first occurs in the LSI 1.
申请公布号 JPS6448136(A) 申请公布日期 1989.02.22
申请号 JP19870205423 申请日期 1987.08.19
申请人 FUJITSU LTD 发明人 OKAMOTO TETSUO
分类号 G06F11/00 主分类号 G06F11/00
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