发明名称 CACHE MEMORY CONTROL SYSTEM FOR PARALLEL COMPUTERS
摘要 PURPOSE:To reduce the overhead for inter-processor communication and data relaying, by transferring data to a cell of the access request source if desired data exists in the cache memory on a cell which the data access request passes. CONSTITUTION:Each cell 2-1 is provided with a cache memory 5-i in which data which at least this cell itself requires or data transferred through this cell on demand is held; and if desired data exists on a cache memory 5-k of a cell 2-k which the data access request from a certain cell passes, this data is transferred to the cell which issues the data access request. Thus, the overhead for inter-processor communication in case of data access to another cell or the overhead for data relaying is reduced.
申请公布号 JPS6448166(A) 申请公布日期 1989.02.22
申请号 JP19870205750 申请日期 1987.08.19
申请人 FUJITSU LTD 发明人 ISHIHATA HIROAKI;HARADA YUKO
分类号 G06F15/16;G06F12/08;G06F15/163;G06F15/173;G06F15/80 主分类号 G06F15/16
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