发明名称 |
Seimiconductor memory device having sub bit lines |
摘要 |
A dynamic random access memory includes a memory cell array, sense amplifiers disposed at both sides of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines may be coupled to data busses through middle amplifiers. By use of such a memory architecture, a higher integration of a DRAM can be realized. Also, the handling of super large bit data, i.e. more than 1024 bits becomes possible.
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申请公布号 |
US4807194(A) |
申请公布日期 |
1989.02.21 |
申请号 |
US19870040471 |
申请日期 |
1987.04.20 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
YAMADA, TOSHIO;INOUE, MICHIHIRO |
分类号 |
G11C11/401;G11C11/409;G11C11/4091;G11C11/4097;(IPC1-7):G11C7/02;G11C5/02 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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