| 摘要 |
In integrated circuits having device islands separated laterally by support to polycrystalline regions and a dielectric layer, a shield layer is provided along the side walls at the dielectric layer having an impurity concentration sufficiently greater than the island's impurity concentration to eliminate support bias influence without seriously affecting the PN junction in the island. The shield impurity concentration is less than the region forming a PN junction with the island and preferably is below 1x1013 ions/cm2 and a peak impurity concentration less than 5x1016 ions/cm3.
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