摘要 |
<p>PURPOSE:To prevent a gate control signal from appearing in output, by providing an N-channel FET and a P-channel FET such that they have an identical gate width and an identical amount of coverage of the gates. CONSTITUTION:A sample-and-hold circuit comprises an N-channel FET and a P-channel FET whose source and drain are connected to the source and drain of the N-channel FET, respectively, said FETs having an identical gate width and an identical amount of coverage of the gates. Accordingly, even if positional deviation of mask or any other problem occurs, the FETs are allowed to have balanced gate capacitances, whereby any noise due to gate capacitance is cancelled and variance in gate capacitance can be reduced substantially.</p> |