发明名称 |
Active load for emitter coupled logic gate |
摘要 |
An active load for a CML or ECL logic gate for substantially increasing the speed of the gate comprises a transistor having its base coupled to its collector by a first resistor, and its collector-emitter path coupled in series with a second resistor. This load provides an inductive impedance when the small signal emitter resistance is less than the sum of the resistance of the base and the first resistor, causing a peaking effect resulting in high switching speed.
|
申请公布号 |
US4806796(A) |
申请公布日期 |
1989.02.21 |
申请号 |
US19880174269 |
申请日期 |
1988.03.28 |
申请人 |
MOTOROLA, INC. |
发明人 |
BUSHEY, THOMAS P.;HWANG, BOR-YUAN |
分类号 |
H03K19/013;H03K19/086;(IPC1-7):H03K19/086 |
主分类号 |
H03K19/013 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|