发明名称 Booth's multiplier
摘要 In Booth's method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PPi (Yi, Yi+1, Yi+2); partial products PDi are formed separately in sequence by multiplying X by each of decoded partial multiplier values Vpp decoded in accordance with Booth theory; and all the partial products PDi are accumulatively added to obtain the product. To increase the processing speed twice in spite of a relatively simple circuit configuration, two partial products of X and Vpp are formed simultaneously in sequence and added to obtain a partial product sum PSi, and all the two partial product sums are accumulatively added to obtain a final result.
申请公布号 US4807175(A) 申请公布日期 1989.02.21
申请号 US19870022968 申请日期 1987.03.06
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TOKUMARU, TAKEJI;KISHIGAMI, HIDECHIKA
分类号 G06F7/533;G06F7/52;G06F7/527;(IPC1-7):G06F7/52 主分类号 G06F7/533
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