发明名称 FLOATING POINT ARITHMETIC UNIT
摘要 PURPOSE:To realize the high-speed processing with a simple program for a floating points arithmetic unit by always converting an exponent part into an integer with extraction of only the exponent part out of the input value and subtraction of an offset component in case the exponent part is extracted in a process where the logarithm value is calculated from the number of floating points. CONSTITUTION:A logical arithmetic circuit 111 adds the floating point obtained from conversion of types to the value of a mantissa part obtained from reference to a table. A register 112 loads the input value as well as the arithmetic result of the circuit 111. An exponent extracting means 113 subtracts an offset component from the bit length of the exponent part of the input value loaded to the register 112 and turns the exponents part into an integer with an arithmetic operation. At the same time, the means 113 delivers selectively the result of said arithmetic operation to a type converting circuit 114. Thus the conversion of floating points is attained and the exponent part is extracted with an arithmetic operation. As a result, a program is simplified and the processing speed is increased for a floating points arithmetic unit.
申请公布号 JPS6446128(A) 申请公布日期 1989.02.20
申请号 JP19870202101 申请日期 1987.08.13
申请人 FUJITSU LTD 发明人 KURIHARA HIDEAKI
分类号 G06F7/00;G06F7/76 主分类号 G06F7/00
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