| 摘要 |
PURPOSE: To provide a central processing unit(CPU) with a variable length instruction, various addressing modes, etc., by adopting the design of a pipeline and a microprogram and preparing an extremely compact microcode. CONSTITUTION: The CPU 10 consists of a memory control module 12 and a data bus module 14. The practical execution of a program instruction is controlled by the module 14 and the module 12 acts as an interface between the module 14 and a system bus 20. Communication between both the modules 12, 14 is executed through a memory control bus 16 and a memory data bus 18. The module 12 is a microprogrammed device to be driven asynchronously with the module 14. In additon to an interface function between the CPU 10 and the bus 20, the module has also a function for converting a virtual address obtained from the module 14 into a physical address, an instruction prefetching function and a data caching function.
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