发明名称 DIGITAL-ANALOG CONVERTER
摘要 PURPOSE:To improve the accuracy, by DA-converting sequentially a digital data at each unit weighting from the start of the weighting operation to its end, so as to suppress the increase in the changing step width of an analog output because of the increase in the weighting amount. CONSTITUTION:In doubling the weighting to a command pulse control section 10 and an FB(feedback) pulse control section 11 (N=2), the count of counters 12, 13 is progressed respectively by 2N, i.e., 4-step at each application of a positive command signal COMP or a positive FB pulse FBP, and the count is operated by 2-step only when the command input or the FB input is zero. Since an output data of a full adder 14 is obtained at the count of the counters 12, 13, the digital data to a DA converting section 15 is revised at each T/N period, where T is the revised period of the command input and/or the FB input and N is the multiple of weighting, and the changing step width of an analog signal is not increased even if the weighting multiple N is increased.
申请公布号 JPS5945715(A) 申请公布日期 1984.03.14
申请号 JP19820155821 申请日期 1982.09.09
申请人 HITACHI SEISAKUSHO KK 发明人 YOSHIHARA MINORU;TSUJI YUKIROU;OOKAWA TADASHI
分类号 H03M1/66;H03M1/68 主分类号 H03M1/66
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