| 摘要 |
<p>PURPOSE: To utilize an already set transmission rate more satisfactorily by performing a data reducing process for a control or synchronizing signal. CONSTITUTION: An image signal encoder for an FBAS signal includes an A/D converting circuit 26, an evaluating circuit 28, a sampling standard converter 30, a data reducing circuit 32, a sequence control unit 34, and a parallel-series converter 36. The FBAS signal is transmitted to the A/D converting circuit 26 and evaluating circuit 28 through an input terminal 24. The evaluating circuit 28 has a synchronizing signal separation stage 62, a PLL 64 which generates a clock pulse signal, a synchronizing signal processing means 66, and a synchronizing word encoder 68. The data reducing circuit 32 has an encoder 56, a multiplexer 58, and a buffer memory 60 and performs the data reduction processing to the control or synchronizing signal.</p> |
