| 摘要 |
PURPOSE:To contrive to execute the processing at a high speed, and also, to softly cope with a complicated processing, as well, by using a memory in which two ports of a serial port and a parallel port can be inputted and outputted independently to and from a local memory and a main memory. CONSTITUTION:A first ring in which plural data flow processors 21-28 and an interface circuit 31 are connected by pipeline buses 201-209 of a single direction becomes a processor module 11 of one unit, and plural pieces of processor modules 11-14 are connected by pipeline buses 106-109 of a single direction through the interface circuit 31 and form a second ring. Also, this processor is constituted by containing a bidirectional system bus 110 to which each interface circuit 31, one 2-port main memory 19 and one host processor 10 are connected, and local memories 15-18 of 2 ports which are connected to the interface circuit 31 by a parallel input/output port, connected to a main memory 19 by a serial input/output port, and provided on every processor module 11-14. In such a way, the processing can be executed at a high speed, and also, this processor can cope softly with a complicated processing, as well. |
