| 摘要 |
<p>PURPOSE:To have priority to a DMA transferring and to have priority to a processing besides a DMA by providing a register to be able to arbitrarily set a DMA transferring cycle number and an instruction executing cycle number and a register to count the DMA transferring cycle number and the instruction executing cycle number. CONSTITUTION:Registers 1 and 3 to be able to arbitrarily set the DMA transferring cycle number and the instruction executing cycle number and count registers 2 and 4 to count the respective cycle numbers are provided. The DMA transferring cycle number and the instruction executing cycle number are controlled by the counted values of the count registers 2 and 4. Thus, a flexible correspondence can be attained to the request of the processing to have priority to the DMA transferring processing or the processing to have priority to the program processing besides the DMA.</p> |
