| 摘要 |
PURPOSE:To make it possible to freely set a lag time by a method wherein a gate array circuit is composed of an inner cell region and an outer cell region, and the driving circuit of the outer cell region is used as a delay circuit. CONSTITUTION:A two-input AND circuit 10 and non-inverter circuits 11 and 12 are arranged on an inner cell region 1, the input buffer circuit 22 and the outer buffer circuit 31 are connected and they are assigned to the delay circuit 3 inserted between the one input of the two input AND circuit 10 and the non- inverter circuit 11. In ordinary circumstances, the delay time of the output buffer circuit is proportioned to the load capacity. Accordingly, a capacitor 70 and the like is added to the adjusting terminal 60 with which the connected point of the output buffer circuit 31 and the input buffer circuit 22 is led out to outside. As a result, the lag time can be adjusted substantially. |
