| 摘要 |
<p>PURPOSE:To contrive the reduction of the number of transistors by providing a first NAND gate circuit in which a single phase clock becomes a first input and the output of a second NAND gate circuit becomes a second input, and a second NAND gate circuit in which the output of a first inverter circuit becomes a first input and the output of a first NAND circuit becomes the second input. CONSTITUTION:The titled circuit contains NAND gate circuits 1, 2 of two inputs and inverter circuits 3, 4 and 5. These NAND gate circuits 1, 2 are not a complete CMOS constitution, but constituted as a pseudo NAND gate circuit. The NAND gate circuit 1 is constituted so that a single phase clock becomes the first input, and the output of the NAND gate circuit 2 becomes the second input, and the NAND gate circuit 2 is constituted so that an output of the inverter circuit 5 becomes the first input, and an output of the NAND gate circuit 1 becomes the second input. This clock generating circuit does not necessitate an inverter circuit for delaying a signal, and accordingly, the number of transistors can be reduced.</p> |
