发明名称 |
Three-state complementary MOS integrated circuit |
摘要 |
In a three-state complementary MOS integrated circuit having an output circuit comprising a P-channel MOS transistor and an N-channel MOS transistor, part of a pre-output stage circuit between the gate inputs of the P-channel MOS transistor and the N-channel MOS transistor of the output circuit comprises a parallel circuit of a first series circuit and a second series circuit, each of the first series circuits comprising a P-channel MOS transistor to which the control signal is applied and an N-channel MOS transistor to which the in inverted control signal is applied. When the control signal and the inverted control signal are at the same potential, either the P-channel MOS transistors or the N-channel MOS transistors of the parallel circuit are off. Accordingly totempole current through the pre-output stage circuit is avoided.
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申请公布号 |
US4804867(A) |
申请公布日期 |
1989.02.14 |
申请号 |
US19870119086 |
申请日期 |
1987.11.10 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OKITAKA, TAKENORI;MIYAZAKI, YUKIO |
分类号 |
H03K19/0175;H03K19/00;H03K19/003;H03K19/094;H03K19/096;(IPC1-7):H03K3/295;H03K3/354;H03K4/48;H03K17/16 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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