Detector logic circuit for a sychronous transmission system for data comprising ternary symbols and controlled partial response class 1, N=2 type intersymbol interference

摘要

A detector logic circuit restores the value 0 or +/-1 of a ternary symbol converted into a signal on five levels 0, +/-1 and +/-2 as a result of class 1, type n=2 partial response transmission. Employing only binary logic circuits, it is connected to the output of a comparator which has four thresholds and which delivers a value representing the receive level by four binary signals. Two of these signals indicate positive overshooting of extreme and intermediate positive thresholds. The other two indicate negative overshooting of negative extreme and intermediate thresholds. The circuit delivers the values of the ternary symbols detected in the form of two binary components which are available at the output and stored for the duration of a symbol by two flip-flops. Both are generated by combinational logic devices of similar design utilizing OR and NOR gates.