| 摘要 |
PURPOSE:To prevent punch through of data due to the overlapping of clock signals by varying the output of 1st and 2nd bits synchronously with each of a biphase clock. CONSTITUTION:Circuit blocks U01-U04 are all master-slave D flip-flops the same in constitution. Then biphase clock signals phi1, phi2 are inputted and the 1st bit output and the 2nd bit output are varied respectively with 1st and 2nd phases of biphase clock signals. The operating speed of a counter circuit is halved in such a way and no signal transmission/reception of the 1st and 2nd bits exists and its own system is controlled by the biphase clock, then punch through of the data due to an overlapped clock signal is prevented. |
