| 摘要 |
PURPOSE:To simplify the constitution of a switching circuit for data transfer timing and to avoid the occurrence of data errors, by inverting a clock pulse in accordance with a fact whether the leading edge (trailing edge) of the clock pulse is kept or not within a specific period of a jitter area, etc., of an advance clock pulse. CONSTITUTION:The input data DT1 is switched synchronously with the leading edge of an input clock CK1. In a period T1 the leading edge of an output clock CK0 is not kept within a jitter are Tj of the data DT1 and the clock CK1. Thus the output signal Sc of a phase comparator 1 is set at L and a timing pulse generating circuit 2 outputs the pulse CK0 as it is in the form of a timing pulse ST. A sampling circuit 3 samples and outputs the data DT1 at the leading edge of the pulse ST. In a period T2 the leading edge of the pulse CK0 is kept within the area Tj and the signal Sc is set at H. Then the circuit 2 inverts the pulse CK0 into the pulse ST and the circuit 3 samples and outputs the data DT1 at the leading edge of the pulse ST similarly to the period T1. |
