| 摘要 |
PURPOSE:To obtain the access of a high speed by providing reset signal generating circuits to respectively generate first and second reset signals based on the change of the input address signals of first and second input address signal groups and independently executing the reset of the pair of data bus lines with the first and second reset signals respectively. CONSTITUTION:The titled device provides a first reset signal generating circuit RE101 to generate a first reset signal phi101 based on the change of the input address signals of first input address signal groups A0-Ai and a second reset signal generating circuit RE102 to generate a second reset signal phi102 based on the change of second input address signals Ai+1-Ai+j and the pair of data bus lines DB and DBB can be independently reset with the first reset signal phi101 and the second reset signal phi102 respectively. Thus, the access of the high speed can be obtained. |
