| 摘要 |
<p>The system comprises a shift register (21), a control latch unit (22), a channel number identification unit (24), a timing control unit (25) and a demultiplexing latch unit (26). Serial input data (1) are converted into parallel data (SR1, SR2, SRn) and an output of a certain channel (SRn) is latched, in response to a fixed timing signal (PH1). According to the difference (k-n) between the identified channel number (k); and that at the transmitter (n), the timing of the demultiplexing latch unit is controlled so that the outputs (CH1, CH2, ---CHn) correspond to the transmitted signals.</p> |
