| 摘要 |
A method, in which the formation of a first metallization level (a) is followed by the deposition of a first and a second isolating layer (b and c), by a selective etching step of the second isolating layer with respect to the first layer (d), the planarization of the structure thus obtained by a sacrificial layer and by the etching of this sacrificial layer down to the level of the second isolating layer (f), the selective etching step between these different layers so as to merge at the first metallization level with respect to a metallization and to ensure simultaneously the isolation between metallization levels with respect to a crossing (g) and finally the formation of the second metallization level (h). This method of quasi self-alignment eliminates a photo-lithographic step and ensures a substantial increase in integration density and in reliability of the circuit.
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