| 摘要 |
PURPOSE:To attain high speed packet multiplexing by providing a reception packet FIFO memory and a transmission packet FIFO memory between a data communication procedure controller and a data bus and using the hardware so as to manage the packet buffer memory. CONSTITUTION:Reception packet FIFO memories 21-2n and transmission packet FIFO memories 31-3n are provided between data communication procedure controller 11-1n and a data bus 6 respectively to transfer packet data with the packet buffer memory 4 via the data bus in the unit of packets as a badge job. Moreover, a packet buffer management controller 5 transmits/receives a packet transfer control signal with the data communication procedure controllers 11-1n to allow the hardware to manage the packet buffer memory 4. Thus, the number of times of data bus access contention is less and high speed packet multiplexing is attained.
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