| 摘要 |
An EEPROM cell for a memory device comprises a pair of bit lines each including a floating-gate MOS transistor such that a selected one of the transistors can be charged while the other is in uncharged condition by applying a higher voltage to a corresponding one of the bit lines and a lower voltage to the other bit line. Information stored in such a cell can thus be rewritten simply by applying a high voltage to one of the pair of its bit lines without carrying out a time-consuming ERASE mode of operation.
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