发明名称 TIMING PULSE GENERATING CIRCUIT
摘要 <p>PURPOSE:To constitute the titled circuit inexpensively without using a ROM by constituting the circuit by a counter circuit, a register, a comparator circuit and a flip-flop capable of being subject to large scale circuit integration easily. CONSTITUTION:The counter circuit 1 is operated by a system clock 101. A leading point comparator circuit 4 compares an output of the counter circuit 1 with a content of a leading point register 2 and outputs a pulse when the both are coincident, and a leading point comparator circuit 5 compares an output of the counter circuit 1 with a content of a leading point register 3 and outputs a pulse when the both are coincident. Then the flip-flop circuit 6 is set by the output of the circuit 4 and reset by the output of the circuit 5 and outputs a timing pulse 102. Thus, an optical timing pulse is generated without the need for a ROM and the large scale circuit integration using a gate array is realized with the circuit constitution without any modification, the scale of the gate is not increased and low cost is realized.</p>
申请公布号 JPS6436116(A) 申请公布日期 1989.02.07
申请号 JP19870190083 申请日期 1987.07.31
申请人 NEC CORP 发明人 KAKIHARA ITARU
分类号 H03K5/00;G06F1/06;H03K5/156 主分类号 H03K5/00
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