| 摘要 |
PURPOSE:To enable size reduction and high integration of MOS transistors by providing a vertical MOS FET on the opposed side parts of a projecting part, and connecting these MOS transistors in parallel to form one MOS transistor. CONSTITUTION:On the two opposed sides of the sides of a projecting part selectively formed on the surface of a substrate 1, gate electrodes 51, 52 are formed so as to face each other through a gate insulating film, a first impurity diffusion region 6 for the source or drain region is formed on the top of a projecting part 1' of the gate electrodes 51, 52, and second impurity diffusion regions 71, 72 for the drain or source region are formed in the perimetry of the bottom of the projecting part 1'. After an inter-layer insulating film is formed on the upper surface of the substrate and a contact hole is formed in the insulating film, a metal wiring is formed, and the second impurity diffusion regions 71, 72 are electrically connected with each other. With this, the height of the projecting part 1' can be set so that a short channel effect or the like does not occur even if the size is reduced. |
