Storage registers with charge packet accumulation capability, as for solid-state imagers

摘要

A CCD storage register for storing an area array of picture elements in a solid-state imager comprises a first set of charge transfer channels arranged in a parallel array with intervening spaces. Respective ones of a second set of charge transfer channels are located in spaces adjacent to the second set of charge transfer channels. Charge transfer stages in adjacent charge transfer channels in said first and second sets of charge transfer channels have corresponding charge storage sites between which connections for charge transfer can be made selectively. This allows shift and add procedures to be carried forward in the CCD storage register. The shift and add capability allows time-delay-integration procedures and true line interlacing procedures, as examples, to be carried forward in the CCD storage register.