发明名称 Transistor-transistor logic circuit
摘要 A transistor-transistor logic circuit, i.e., TTL circuit includes at least one input terminal (IN; IN1, IN2), an output transistor (T10, T1), and elements (1, 2, T11, T12; 3, 4, T2) operatively connected between an input terminal and the base of an output transistor. The elements include a plurality of delay parts, each having a different signal propagation delay time respectively which feed base currents to the base of the output transistor in and at a different times. As a result, a quick change in the output is prevented and thus an overshoot, ringing or noise can be prevented, while realizing an increased driving ability. At the same time, optimum output characteristics can be obtained according to a load to be driven by the TTL circuit.
申请公布号 US4803383(A) 申请公布日期 1989.02.07
申请号 US19870115870 申请日期 1987.11.02
申请人 FUJITSU LIMITED 发明人 HIROCHI, KATSUJI
分类号 H03K17/16;H03K19/003;H03K19/082;H03K19/084;H03K19/088;(IPC1-7):H03K19/003;H03K17/28;H03K17/60 主分类号 H03K17/16
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