发明名称 PHASE LOCKED LOOP APPARATUS
摘要 PURPOSE: To prevent a performance from deteriorating owing to a change of a parameter or a secular change by providing a phase comparator which generates a control signal supplied to an analog oscillator in response to one of an output signal of a analog oscillator and a multi-bit digital oscillation signal. CONSTITUTION: This device is equipped with a digital signal generating means 241 including a digital oscillator 230 which generates a digital oscillation signal representing sampled data consisting of bits having a frequency approximating a predetermined nominal frequency. Further, the device is equipped with a digital phase comparing means 252 which is coupled with a variable oscillator 256 and the digital signal generating means 241 and generates a phase difference signal proportional to the phase difference between an oscillation signal and a single-bit digital signal representing predetermined bits of the digital oscillation signal consisting of the bits and a means 254 which is coupled with the phase comparing means 252 and generates a control signal in response to the phase difference signal. Consequently, this phase-locked clock signal is stably generated.
申请公布号 JPS6436184(A) 申请公布日期 1989.02.07
申请号 JP19880176183 申请日期 1988.07.13
申请人 RCA LICENSING CORP 发明人 BERUNAA NIKURAUSU HAATOMAIYAA
分类号 H04N9/475;H03L7/06;H03L7/08;H03L7/081;H03L7/085;H03L7/099;H03L7/23 主分类号 H04N9/475
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